1. Field of the Invention
The present invention relates to a bipolar transistor suitable for a reference voltage source circuit used as a power source circuit for integrated circuits and the like, and a semiconductor device having the same, and more specifically to a bipolar transistor designed to stabilize reference voltage output when applied in a reference voltage source circuit, and a semiconductor device having the same.
2. Description of the Related Art
It is necessary to raise the relative precision of the element and the absolute precision of the resistance, when providing a semiconductor device with a reference voltage source circuit. Therefore, conventionally, it has been common to manufacture the reference voltage source circuit by means of a bipolar process used very often and chiefly in analog circuits. This is because since an analog circuit was held to be necessary for the reference voltage source circuit, there was no choice but to use a bipolar process.
Recently, however, as circuits have become integrated, analog circuits have also started to be built into CMOS processes used in digital circuits. This has made it necessary to incorporate reference voltage source circuits into the CMOS process.
FIG. 1 is a circuit diagram showing a conventional reference voltage source circuit. The conventional reference voltage source circuit is provides with two PNP transistor groups GQ31 and GQ32, whose collectors and bases are grounded. A resistor RE33 and a resistor RE32 are connected to the emitter of the PNP transistor group GQ32 in series, in that order. Additionally, a resistor RE31 is connected to the emitter of the PNP transistor group GQ31. Further, the input terminals of an amplifier AMP31 are connected to the connection point of the emitter of the PNP transistor group GQ31 and the resistor RE31, and to the connection point of the resistor RE32 and the resistor RE33. The other end of the resistor RE32 and the other end of the resistor RE31 have a common connection, and this connection point is connected to the output terminal of the amplifier AMP31. Further, an output voltage terminal OUT31 is connected to the output terminal of the amplifier AMP31. Note that the amplifier AMP31 is composed of a CMOS transistor and the like.
Both of the PNP transistor groups GQ31 and CQ32 are composed of a plurality of PNP transistors. FIG. 2 is a layout diagram showing a layout of PNP transistors making up the PNP transistor groups GQ31 and GQ32. Below, the reference voltage source circuit described here in FIG. 2 shall be called as a first prior art.
As shown in FIG. 2, the PNP transistor group GQ31 comprises three PNP transistors Q111 through Q113 arrayed in a vertical column, and the PNP transistor group GQ32 comprises nine PNP transistors Q121 through Q129 arrayed in three rows and three columns. In each of the PNP transistors Q111 through Q113 and Q121 through Q129, an emitter electrode 106 is connected to the central portion of an emitter 103. A base 102 is formed around the periphery of the emitter 103, and within base 102, base electrodes 107 are connected on either side of the emitter 103, in the row direction as seen from the emitter 103. A collector 101 is common to each of the PNP transistors, and collector electrodes 108 are connected on either side of the base 102 of each PNP transistor, in the row direction as seen from the base 102. Note that each of the PNP transistors has the same emitter surface area. As the PNP transistor group GQ32 includes the nine PNP transistors Q121 through Q129 while the PNP transistor group GQ31 includes the three PNP transistors Q111 through Q113, the total emitter area of the PNP transistor group GQ32 is three times that of the PNP transistor group GQ31.
The reference voltage Vout output of a conventional reference voltage source circuit constructed in this way is shown in Formula 1 shown below, where the resistance of the resistor RE31 and RE32 is y, the resistance of the resistor RE33 is x, the voltage between the emitter and base of the PNP transistor group GQ31 is VEBGQ31, the total emitter surface area of the PNP transistor group GQ31 is M, the total emitter surface area of the PNP transistor group GQ32 is N, the Boltzmann""s constant is k, the absolute operating temperature is T, the elementary electric charge is q.                     Vout        =                  VEBG31          +                                    y              x                        ·                                          k                ·                T                            q                        ·                                          log                e                            ⁡                              (                                  N                  M                                )                                                                        [Formula  1]            
Thus, reference voltage Vout fluctuates depending on the resistance ratio of the resistors (y/x), and the total emitter area ratio of the transistors (N/M). Consequently, even if the absolute values of the resistance x and y, and total emitter surface area N and M, change, as long as their respective ratios do not change, the reference voltage Vout will be stable. Under these circumstances, since, in the first prior art, the PNP transistor groups Q31 and Q32 are composed of a plurality of transistors, even if a number of these had low levels of precision, the impact on the overall relative precision would be slight. For this reason, as described above the reference voltage Vout is stable. Consequently, constructing a transistor group from a plurality of transistors facilitates the manufacture of a reference voltage source circuit with stable reference voltage.
Additionally, as the number of each electrode is kept down, the amount of space they take up on the chip is small. An array of the PNP transistors as shown in FIG. 2 is described, for example, in the literature xe2x80x9cA Precision Curvature-Compensated CMOS Bandgap Referencexe2x80x9d (cited from: P634-643 IEEE JURNAL OF SOLID-STATE CIRCUITS, VOL. SC-18, No. 6, December 1983). The reference voltage source circuit described in this literature provides a separate external resistor in order to compensate from the gap from DC operation.
In another prior art from the literature, a reference voltage source circuit with a construction in which a plurality of transistors arrayed in a column have a collector in common is described in xe2x80x9cA Precision CMOS Bandgap Referencexe2x80x9d (cited from: IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL, SC-19, No. 6, December 1984 P1014-1021). The conventional reference voltage source circuit described below shall be called a second prior art. FIG.3 shows a layout diagram of the reference voltage source circuit according to the second prior art.
Two transistor groups GQ41 and GQ42 are provided in the second prior art. The transistor group GQ41 is made up of five transistors Q131 through Q135 forming a column, and the transistor group GQ42 is made up of twenty-five transistors Q141 through Q165 forming five rows and five columns. Consequently, the total emitter surface area ratio of the transistor group GQ41 to the transistor group GQ42 is 1:5.
Note that while the above-mentioned reference in the literature does not describe the electrode arrangement and the like of each transistor in detail, it is thought that the five transistors forming a column have a collector 111 in common, and that a base electrode 117 and an emitter electrode 116 in a group of one row are alternately arrayed.
Additionally, Japanese Patent Laid-Open Publication No. Hei. 6-151705 discloses a bandgap generator circuit provided with a transistor group made up of a plurality of transistors in a square formation when seen from the plane. Below, this conventional bandgap generator circuit shall be called as a third prior art.
In the third prior art, the four transistors in a square formation are laid out in a square lattice formation. The four transistors have a collector and a base in common.
In the first prior art, however, since there is a large amount of parasitic resistance on the base and collector in each transistor, there is a problem in that the size of resistors RE31 and RE32 must be increased, and the current flowing through the transistor group GQ31 and GQ32 must be decreased, in order for the transistor group GQ31 and GQ32 to operate in a state approaching an ideal state. That is, increasing the size of the resistors RE31 and RE32 increases the amount of resistance noise generated in proportion to the resistance of these resistors. Additionally, the sealing process of semiconductor chips and the like applies a great deal of stress in the lateral direction of FIG. 2, which warps the surface of the semiconductor chip. This warping acts on the cross-sectional direction of the semiconductor device, and tends to worsen the relative precision of the PNP transistor, as this warping impacts the transistor groups GQ31 and GQ32 in which the PNP transistors are formed in the same depth-wise direction. In particular, if the transistor groups GQ31 and GQ32 are arrayed so that they are elongated along the same direction of this directional warping stress distribution, there is the limitation that output voltage and temperature characteristics become susceptible to fluctuation. Consequently, when designing a semiconductor chip provided therewith, the anisotropy of these characteristics must be taken into account, decreasing the design margin.
Furthermore, in the above-mentioned literature employing this construction, a separate resistor is provided in order to compensate for the gap in PNP transistor characteristics caused by parasitic resistance on the base portion. However, this construction of a compensatory resistor makes the chip area even larger.
Additionally, the second prior art has a problem in that there is a large amount of resistance noise in the resistors consequent to the parasitic resistance on the base and collector is large. Additionally, because the five transistors forming a column are provided with one collector electrode, the parasitic resistance on the collector is different as seen from each transistor, it is difficult to secure a relative precision between each resistance. This results in the following problem: many of the transistors are not in an ideal state, making it impossible to obtain a desired reference voltage output. Furthermore, as with the first prior art, the direction in which warping is generated creates the problem of large fluctuations in the output voltage and temperature characteristics, making it necessary to take this into consideration when designing semiconductor chips. Consequently, as mentioned above, this has the limitation of decreasing the design margin.
Furthermore, in the third prior art, as the four transistors have a collector and a base in common, the parasitic resistance on the base is different between each transistor. For this reason, as with the second prior art, this results in the problem that many of the transistors are not in an ideal state, making it impossible to obtain a desired reference voltage output. Additionally, the reduction of parasitic resistance on the collector and base is not sufficient.
An object of the present invention is to provide a bipolar transistor capable of reducing design limitations and reducing the resistance noise generated by resistors in the case of application to a reference voltage source circuit, and a semiconductor device having the same.
According to one aspect of the present invention, a bipolar transistor comprises a collector layer of a first conductive type, a base layer of a second conductive type formed at a surface of the collector layer, and an emitter layer of the first conductive type formed at a surface of the base layer. An emitter electrode is connected to the emitter layer. Base electrodes are connected to the base layer and surround the emitter electrode. Collector electrodes are connected to the collector layer and surround the base electrodes.
In the present invention, the parasitic resistance on the base and collector is isotropic in comparison with conventional ones, as the emitter electrode is surrounded by the base electrodes, and the base electrodes are surrounded by the collector electrodes. For this reason, the variation in their respective parasitic resistance is lessened. Additionally, the total parasitic resistance is reduced. Consequently, a wide design margin can be secured, while at the same time allowing the resistance of the resistors connected to the bipolar transistor to be lessened in the case of application to a reference voltage source circuit, resulting in reduced resistance noise.
It is preferable that the base layer and emitter layer have a square shape seen from above, and that the emitter layer is provided in the center of the base layer. Selecting this type of shape and layout increases the isotropy of the bipolar transistor.
According to another aspect of the present invention, a semiconductor device comprises a plurality of the bipolar transistors.
Additionally, it is preferable for the collector layer of each of the bipolar transistors to be made up of a single semiconductor layer. This construction makes it possible to secure a high emitter surface relative precision, facilitating the acquisition of a stable reference voltage output when applied to a reference voltage source circuit.
Furthermore, it is preferable for the bipolar transistors to be arrayed in a matrix formation. It is more desirable for the bipolar transistors to be arrayed in a square formation with the same number arrayed in the vertical direction as the horizontal direction. This square-formation layout makes it possible to obtain high isotropy on a chip.
Furthermore, the bipolar transistors may be defined into two or more groups, and within each group, the collector electrodes may be connected to one another, the base electrodes may be connected to one another, and the emitter electrodes may be connected to one another. In this case, when the bipolar transistors arrayed in a square formation is partitioned by a diagonal line of the square, it is preferable that bipolar transistors in each of said groups are arrayed in linear symmetry about said diagonal line. It is possible to ensure isotropy in at least the two 45-degree angle directions from that diagonal line.